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ACEX1 Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers

No. de pieza ACEX1
Descripción Electrónicos  Programmable Logic Device Family
PDF  86 Pages
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Fabricante Electrónico  ETC [List of Unclassifed Manufacturers]
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ACEX1 Datasheet(HTML) 24 Page - List of Unclassifed Manufacturers

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24
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the preset and clear inputs for the desired functionality.
Figure 12. ACEX 1K LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
Asynchronous Preset & Clear
Asynchronous Load without Clear or Preset
labctrl1
(Asynchronous
Load)
PRN
CLRN
DQ
NOT
NOT
labctrl1
(Asynchronous
Load)
Asynchronous Load with Clear
labctrl2
(Clear)
PRN
CLRN
DQ
NOT
NOT
(Asynchronous
Load)
Asynchronous Load with Preset
NOT
NOT
PRN
CLRN
DQ
labctrl1 or
labctrl2
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
PRN
CLRN
DQ
PRN
CLRN
DQ
VCC
Chip-WideReset
Chip-Wide Reset
data3
(Data)
labctrl1
labctrl2
(Preset)
data3
(Data)
data3
(Data)
labctrl1 or
labctrl2
labctrl1
labctrl2



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