6

PS8613A

07/15/03

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PI6C2409

Zero Delay Clock Buffer

SwitchingWaveforms

tlow

thigh

VDD/2

VDD/2

VDD/2

tF

tR

0.8V

2.0V

0.8V

2.0V

OUTPUT

0V

3.3V

VDD/2

VDD/2

VDD/2

VDD/2

VDD/2

VDD/2

tSK(O)

OUTPUT

OUTPUT

t0

INPUT

OUTPUT

tSK(D)

OUTPUT Device 1

OUTPUT Device 2

Duty Cycle Timing

All Outputs Rise/Fall Time

Output-Output Skew

Input-Output Propagation Delay

Device-Device Skew

tDC =

thigh

thigh+tlow

VDD

CLOAD

VDD

GND

GND

CLK out

OUTPUTS

Test Circuit 1

Test Circuit 2

0.1µF

0.1µF

VDD

10pF

VDD

GND

GND

CLK out

OUTPUTS

0.1µF

0.1µF

1k

Ω

1k

Ω