ADCS9888 datasheet(19/34 Pages) NSC

19 / 34 page

Configuration Register Descriptions (Continued)

Address

(Hex)

Write/Read

or Read Only

Bits

POR Value

Name

Bit Name/Description

0BH

W/R

7:1

1000000*

Red Offset

Controls the DC offset correction prior to analog to

digital conversion. Default setting is for no offset.

Settings higher than 10H make resulting image less

bright, settings lower than 10H makes image more

bright. Absolute offset amount is also dependent on

setting of corresponding gain channel. See description

of Offset/Gain functions for more information.

OCH

W/R

7:1

1000000*

Green Offset

ODH

W/R

7:1

1000000*

Blue Offset

OEH

W/R

0*******

Sync Control

Hsync Polarity Override. 0 = polarity determined by

chip, 1 = polarity set by Register 0EH, bit 6.

*1******

Hsync Input Polarity. 0 = active low, 1 = active high.

**0*****

Hsync Output Polarity. 0 = logic high HSOUT, 1 = logic

low HSOUT.

***0****

Active Hsync Override. 1 = Hsync source determined by

user setting in Register 0EH, bit 3. 0 = determined by

chip results in Register 14H, bit 6.

****0***

Active Hsync Select. 0 = HSYNC input is Hsync source.

1 = output of SOGIN sync slicer is Hsync source. This

bit only takes effect if Register 0EH bit 4 is 1, or if both

Hsync sources are active.

*****0**

Vsync Output Invert. 0 = inverted. 1 = not inverted.

******0*

Active Vsync Override. 1 = source determined by user

setting in Register 0EH, bit 0. 0 = source determined by

chip results in Register 14H, bit 3.

*******0

Active Vsync Select. 0 = VSYNC input is Vsync source.

1 = Sync separator output is Vsync source. This bit only

has effect if Register 0EH, bit1=1.

ADCS9888 Datasheet(PDF) 19 Page - National Semiconductor (TI)

ADCS9888 Datasheet(HTML) 19 Page - National Semiconductor (TI)

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