IRCC datasheet(7/79 Pages) SMSC

7 / 79 page

Table 7 - IRCC-Specific Chip-Level Controls

NAME

SIZE (BITS)

TYPE

DESCRIPTION

DMA Channel

Input

ISA DMA Channel Number

IRQ Level

Input

ISA Interrupt Level

DMA Channel

4-bit bus from a chip-level configuration register,

used to identify the current IrCC DMA channel

number. The value appears in the upper nibble

of IrCC Register Block Three, Address Four.

IRQ Level

4-bit bus from a chip-level configuration register,

used to identify the current IrCC IRQ level. The

value appears in the lower nibble of IrCC

Table 8 - Legacy Chip-Level Controls

NAME

SIZE (BITS)

TYPE

DESCRIPTION

Tx Polarity

Input

Output Mux. Transmit Polarity

Rx Polarity

Input

Output Mux. Receive Polarity

Half Duplex

Input

16550A UART Half Duplex Control

IR Mode

Input

IR Mode Register Bits

IR Location

Input

IR Option Register Location Bits

Tx Polarity

Typically part of a 16550A Serial Port Option

The value also appears in IrCC

Rx Polarity

Typically part of a 16550A Serial Port Option

The value also appears in IrCC

Half Duplex

Typically part of a 16550A Serial Port Option

The value also appears in IrCC

IR Mode

Typically part of a 16550A Serial Port Option

Block Control bits 3-5, Register Block One,

Address Zero.

IR Location

Typically part of a 16550A Serial Port IR Option

bits, Register Block One, Address One.

NOTE: These legacy controls are uniformly

updated in the IrCC and the Top-level Device

Configuration Registers only when either set of

registers are explicitly written using IOW or

following a device-level POR.

IrCC software

resets will not affect the legacy bits.

IRCC Datasheet(PDF) 7 Page - SMSC Corporation

IRCC Datasheet(HTML) 7 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Descarga

Enlace URL