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ICS950812

0542G—08/21/03

All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is

NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is

configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks.

The PCI group should lag 3V66 by the standard skew described below as Tpci.

The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation

value.

Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship

Group to Group Skews at Common Transition Edges: Buffered Mode

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

66MHz_IN 66MHz_OUT

1,2

Tpd

Propogation delay from

66MHz_IN to 66MHz_OUT (2:0)

2.5

2.9

4.5

ns

66MHz_OUT to PCI

1,2

Tpci

66MHz_OUT (2:0) leads 33 MHz

PCICLK

1.5

3.5

ns

E_PCICLK to PCICLK Skews

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

E_PCICLK1 (pin 11)=0

E_PCICLK3 (pin 13)=1

0.3

0.5

0.7

ns

E_PCICLK1 (pin 11)=1

E_PCICLK3 (pin 13)=0

0.8

1.0

1.2

ns

E_PCICLK1 (pin 11)=1

E_PCICLK3 (pin 13)=1

1.3

1.5

1.7

ns

E_PCICLK to PCICLK

1

66MHz_IN

66MHz_OUT

3V66

Tpd

Tpci

No Relationship

E_PCICLK (3,1)

Tepci

PCICLK_F (2:0) PCICLK (6:0)