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CS61575 Datasheet(PDF) 6 Page - Cirrus Logic |
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CS61575 Datasheet(HTML) 6 Page - Cirrus Logic |
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6 / 44 page  E1 SWITCHING CHARACTERISTICS (TA = -40 °C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 26) fc - 8.192000 - MHz TCLK Frequency ftclk -2.048 - MHz TCLK Pulse Width (Note 29) tpwh2 150 - 340 ns ACLKI Duty Cycle tpwh3/tpw3 40 - 60 % ACLKI Frequency (Note 30) faclki -2.048 - MHz RCLK Duty Cycle (Note 31) tpwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 32) tr - - 85 ns Fall Time, All Digital Outputs (Note 32) tf - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 33) tsu1 100 194 - ns RDATA Valid Before RCLK Falling (Note 34) tsu1 100 194 - ns RPOS/RNEG Valid Before RCLK Rising (Note 35) tsu1 100 194 - ns RPOS/RNEG Valid After RCLK Falling (Note 33) th1 100 194 - ns RDATA Valid After RCLK Falling (Note 34) th1 100 194 - ns RPOS/RNEG Valid After RCLK Rising (Note 35) th1 100 194 - ns T1 SWITCHING CHARACTERISTICS (TA = -40 °C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 26) fc - 6.176000 - MHz TCLK Frequency ftclk -1.544 - MHz TCLK Pulse Width (Note 29) tpwh2 150 - 500 ns ACLKI Duty Cycle tpwh3/tpw3 40 - 60 % ACLKI Frequency (Note 30) faclki -1.544 - MHz RCLK Duty Cycle (Note 31) tpwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 32) tr - - 85 ns Fall Time, All Digital Outputs (Note 32) tf - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 33) tsu1 150 274 - ns RDATA Valid Before RCLK Falling (Note 34) tsu1 150 274 - ns RPOS/RNEG Valid Before RCLK Rising (Note 35) tsu1 150 274 - ns RPOS/RNEG Valid After RCLK Falling (Note 33) th1 150 274 - ns RDATA Valid After RCLK Falling (Note 34) th1 150 274 - ns RPOS/RNEG Valid After RCLK Rising (Note 35) th1 150 274 - ns Notes: 29. The transmitted pulse width does not depend on the TCLK duty cycle. 30. ACLKI provided by an external source or TCLK. 31. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 32. At max load of 1.6 mA and 50 pF. 33. Host Mode (CLKE = 1). 34. Extended Hardware Mode. 35. Hardware Mode, or Host Mode (CLKE = 0). CS61574A CS61575 6 DS154F2 |
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