Data Sheet

AD9286

Rev. C | Page 7 of 27

N – 1

N + 1

N – 11

M – 10

N – 10

M – 9

N – 9

M – 8

M – 7

N – 8

N – 7

N + 2

N + 4

N + 5

N + 3

M + 5

M + 4

M + 3

M + 1

M + 2

M

N

M – 1

VIN1+, VIN1–

VIN2+, VIN2–

CLK+

CLK–

DCO+, DCO–

DATA

Figure 3. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 0

N – 11

M – 11

M – 10

N – 10

M – 9

N – 9

M – 8

M – 7

N – 8

CLK+

CLK–

DCO+, DCO–

DATA

AUXCLK+

AUXCLK–

N – 1

N + 1

N + 2

N + 4

N + 5

N + 3

M + 5

M + 4

M + 3

M + 1

M + 2

M

N

M – 1

VIN1+, VIN1–

VIN2+, VIN2–

Figure 4. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK in Phase