CS5371/CS5372

6

DS255PP2

Notes: 18. If MCLK is removed, the CS5372 enters a micro power state.

19. Excludes MCLK input, MCLK should be driven with a signal having rise/fall times of 25 ns or faster.

20. MSYNC latched on MCLK falling edge, data output on next MCLK rising edge.

Parameter

Symbol

Min

Typ

Max

Unit

MCLK Frequency

(Note 18)

0.1

2.048

2.2

MHz

MCLK Duty Cycle

40

-

60

%

MCLK Jitter (In-band, Aliased in-band)

-

-

300

ps

MCLK Jitter (Out-of-band)

-

-

1

ns

Rise Times:

Any Digital Input

(Note 19)

Any Digital Output

-

-

-

50

50

100

ns

ns

Fall Times:

Any Digital Input

(Note 19)

Any Digital Output

-

-

-

50

50

100

ns

ns

MSYNC Setup Time to MCLK falling

(Note 20)

20

-

-

ns

MSYNC Hold Time after MCLK falling

20

-

-

ns

MCLK rising to Valid MFLAG

-35

65

ns

MCLK rising to Valid MDATA

-60

90

ns

2.7 V

0.3 V

2.7 V

0.3 V

Figure 1. Rise and Fall Times

MFLAG

MDATA

t mdv

t mdv

VALID DATA

VALID DATA

MCLK

t mss

MSYNC

t mfh

t msh

Figure 2. CS5372 Interface Timing