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STM32F779IGH7 Datasheet(PDF) 217 Page - STMicroelectronics |
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STM32F779IGH7 Datasheet(HTML) 217 Page - STMicroelectronics |
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217 / 255 page ![]() DocID028294 Rev 4 217/255 STM32F777xx STM32F778Ax STM32F779xx Electrical characteristics 224 Figure 75. Quad-SPI timing diagram - SDR mode Figure 76. Quad-SPI timing diagram - DDR mode 5.3.32 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 120 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Table 120. DCMI characteristics(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 DCMI_PIXCLK Pixel clock input - 54 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - ns th(DATA) Data input hold time 0.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 2.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 3 - |
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