TNETV2685FIBZUT9 datasheet(171/191 Pages) TI1

171 / 191 page

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.19.4 Ethernet Subsystem Timing

Table 6-82. Ethernet Subsystem Timing Requirements

PARAMETER(1)

MIN

NOM

MAX

UNITS

t01

REFCLKP/N period, mode

x 10 mode

x 20 mode

x 25 mode

t02

REFCLKP/N duty cycle

t03

REFCLKP/N rise/fall

700

t04

PLL Clock Period, x n Mode

t01 / n

t05

PLL power up

1 + 200 * C

μs

(1)

C = REFCLKP/N period in

μs.

REFCLKP/N Jitter and PLL Loop Bandwidth

Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby

impairing system performance. A good quality, low jitter reference clock is necessary to achieve

compliance with most if not all physical layer standards (see Table 6-83).

Table 6-83. REFCLKP/N Jitter Requirements for Standards Compliance

Standard

Line Rate (Gbps)

Total REFCLKP/N Jitter (within PLL bandwidth)

Gigabit Ethernet

1.25

50 ps pk-pk

Peripheral Information and Electrical Specifications

171

Submit Documentation Feedback

Product Folder Link(s): TMS320DM647 TMS320DM648

TNETV2685FIBZUT9 Datasheet(PDF) 171 Page - Texas Instruments

TNETV2685FIBZUT9 Datasheet(HTML) 171 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL