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TNETV2685FIBZUT7 Datasheet(PDF) 94 Page - Texas Instruments |
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TNETV2685FIBZUT7 Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 191 page  TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com Table 6-23. Pin Behaviors at Reset (continued) Pin Name Reset Group DDR_RAS DDR2 High Group DDR_WE DDR2 High Group DDR_A00 DDR2 Low Group DDR_A01 DDR2 Low Group DDR_A02 DDR2 Low Group DDR_A03 DDR2 Low Group DDR_A04 DDR2 Low Group DDR_A05 DDR2 Low Group DDR_A06 DDR2 Low Group DDR_A07 DDR2 Low Group DDR_A08 DDR2 Low Group DDR_A09 DDR2 Low Group DDR_A10 DDR2 Low Group DDR_A11 DDR2 Low Group DDR_A12 DDR2 Low Group DDR_A13 DDR2 Low Group DDR_ODT0 DDR2 Low Group DDR_ODT1 DDR2 Low Group DDR_CKE DDR2 Low Group DDR_DQGATE0 DDR2 Low Group DDR_DQGATE2 DDR2 Low Group DDR_BA[0] DDR2 Low/High Group DDR_BA[1] DDR2 Low/High Group DDR_BA[2] DDR2 Low/High Group DDR_CS DDR2 High/Low Group DDR_CLKP Clock DDR_CLKN Clock VP3CLK0/AECLKIN Clock RESETSTAT Reflects POR or RESET value 6.7.9 Reset Electrical Data/Timing NOTE If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor. Table 6-24. Timing Requirements for Reset(1) (2) (see Figure 6-10) 720, 800, 900, 1100 NO. UNIT MIN MAX 5 tw(POR) Pulse duration, POR low(3) 256D ns 6 tw(RESET) Pulse duration, RESET low 24C ns Setup time, boot mode and configuration pins valid before POR high or 7 tsu(boot) 6P ns RESET high (4) (1) C = 1/CLKIN1 clock frequency in ns (2) D = 1/CLKIN2 clock frequency in ns (3) If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use the slower of the CLKIN1,CLKIN2 cycles. (4) P = 1/CPU clock frequency in nanoseconds 94 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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