TNETV6446AINZWT datasheet(109/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.7

Interrupts

The DM6446 device has a large number of interrupts to service the needs of its many peripherals and

subsystems. Both the ARM and C64x+ are capable of servicing these interrupts. All of the device

interrupts are routed to the ARM interrupt controller with only a limited set routed to the C64x+ interrupt

controller. The interrupts can be selectively enabled or disabled in either of the controllers. In typical

applications, the ARM handles most of the peripheral interrupts and grants control, to the C64x+, of

interrupts that are relevant to DSP algorithms. Also, the ARM and DSP can communicate with each other

through interrupts.

6.7.1

ARM CPU Interrupts

The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The DM6446 ARM interrupt controller

prioritizes up to 64 interrupt requests from various peripherals and subsystems, which are listed in

Table 6-20, and interrupts the ARM CPU. Each interrupt is programmable for up to 8 levels of priority.

There are 6 levels for IRQ and 2 levels for FIQ. Interrupts at the same priority level are serviced in order

by the ARM Interrupt Number, with the lowest number having the highest priority. Table 6-21 shows the

ARM interrupt controller registers and memory locations. For more details on ARM interrupt control, see

the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

Peripheral and Electrical Specifications

109

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