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TNETV6446AINZWT Datasheet(PDF) 200 Page - Texas Instruments |
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TNETV6446AINZWT Datasheet(HTML) 200 Page - Texas Instruments |
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200 / 227 page  23 19 18 22 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Table 6-86. Switching Characteristics for I2C Timings (see Figure 6-66) A-513, -594, -810 NO. PARAMETER UNIT STANDARD FAST MODE MODE MIN MAX MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.5 µs Delay time, SCL high to SDA low 17 td(SCLH-SDAL) 4.7 0.6 µs (for a repeated START condition) Delay time, SDA low to SCL low 18 td(SDAL-SCLL) 4 0.6 µs (for a START and a repeated START condition) 19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs 21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 ns 22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low 0 0 0.9 µs 23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs 28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs 29 Cp Capacitance for each I2C pin 10 10 pF Figure 6-66. I2C Transmit Timings CAUTION The DM6446 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/O buffer defined in the I2C specification. Series resistors may be necessary to reduce noise at the system level. 200 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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