TNETV6446AINZWT datasheet(157/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.13.1 Video Processing Front-End (VPFE)

The Video Processing Front-End (VPFE) consists of the CCD Controller (CCDC), Preview Engine,

Resizer, Hardware 3A (H3A) Statistic Generator, and Histogram blocks. Together, these modules provide

DM6446 with a powerful and flexible front-end interface. These modules are briefly described below:

•

The CCDC provides an interface to image sensors and digital video sources.

•

The Preview Engine is a parameterized hardwired image processing block which is used for converting

RAW color data from a Bayer pattern to YUV 4:2:2.

•

The Resizer module re-sizes the input image data to the desired display or video encoding resolution

•

The H3A module provides control loops for Auto Focus (AF), Auto White Balance (AWB) and Auto

Exposure (AE).

•

The Histogram module bins input color pixels, depending on the amplitude, and provides statistics

required to implement various 3A (AE/AF/AWB) algorithms and tune the final image/video output.

The VPFE register memory mapping is shown in Table 6-47.

Table 6-47. VPFE Register Address Range Descriptions

HEX ADDRESS RANGE

ACRONYM

0x01C7 0400 – 0x01C7 07FF

CCDC

VPFE – CCD Controller

0x01C7 0800 – 0x01C7 0BFF

VPFE – Preview Engine/Image Signal Processor

0x01C7 0C00 – 0x01C7 09FF

RESZ

VPFE – Resizer

0x01C7 1000 – 0x01C7 13FF

HIST

VPFE – Histogram

0x01C7 1400 – 0x01C7 17FF

H3A

VPFE – Hardware 3A (Auto-Focus/WB/Exposure)

0x01C7 3400 – 0x01C7 3FFF

VPSS

VPSS Shared Buffer Logic Registers

6.13.1.1 CCD Controller (CCDC)

The CCDC receives raw image/video data from sensors (CMOS or CCD) or YUV video data in numerous

formats from video decoder devices. The following features are supported by the CCDC module.

•

Conventional Bayer pattern formats.

•

Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to an

external timing generator.

•

Interface to progressive and interlaced sensors.

•

REC656/CCIR-656 standard (YCbCr 4:2:2 format, either 8- or 16-bit).

•

YCbCr 4:2:2 format, either 8- or 16-bit with discrete H and VSYNC signals.

•

Up to 16-bit input.

•

Optical black clamping signal generation.

•

Shutter signal control.

•

Digital clamping and black level compensation.

•

10-bit to 8-bit A-law compression.

•

Low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right

edges of each line are cropped from the output.

•

Output range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area).

•

Downsampling via programmable culling patterns.

•

Control output to the DDR2 via an external write enable signal.

•

Up to 16K pixels (image size) in both the horizontal and vertical direction.

The CCDC register memory mapping is shown in Table 6-48.

Peripheral and Electrical Specifications

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