PC87364-XXXSLASHVLA datasheet(104/180 Pages) NSC

104 / 180 page

3.0 System Wake-Up Control (SWC) (Continued)

102

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3.4.25

CEIR Address Shift Register (ADSR)

This register holds the received address to be compared with the address contained in the IRWAD register.

This register is set to 00h on power-up of VPP or software reset.

Location:

Bank 1, Offset 17h

Type:

3.4.26

CEIR Wake-Up Range 0 Registers

These registers define the low and high limits of time range 0. The values are represented in units of 0.1 msec.

For the RC-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. The nominal cell width

is 1.778 msec for a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h respectively (default).

For the NEC protocol, the time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within

this range. The nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h

and 0Dh respectively.

IRWTR0L Register

This register is set to 10h on power-up of VPP or software reset.

Location:

Bank 1, Offset 18h

Type:

R/W

IRWTR0H Register

This register is set to 14h on power-up of VPP or software reset.

Location:

Bank 1, Offset 19h

Type:

R/W

Bit

76543210

Name

CEIR Address

Reset

00000000

Bit

76543210

Name

Reserved

CEIR Pulse Change, Range 0, Low Limit

Reset

00010000

Bit

76543210

Name

Reserved

CEIR Pulse Change, Range 0, High Limit

Reset

00010100

PC87364-XXX/VLA Datasheet(PDF) 104 Page - National Semiconductor (TI)

PC87364-XXX/VLA Datasheet(HTML) 104 Page - National Semiconductor (TI)

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