PC87364 datasheet(13/180 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

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1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY

Table 2 is an alphabetical list of all signals, cross-referenced to additional information for detailed functional descriptions,

electrical DC characteristics, and pin multiplexing. The signal DC characteristics are denoted by a buffer type symbol, de-

scribed briefly below and in further detail in Section 10.2. The pin multiplexing information refers to two different types of

multiplexing:

MUX - Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two

different functions. Each function is associated with different board connectivity, and normally, the function selection

is determined by the board design and cannot be changed dynamically. The multiplexing options must be conﬁgured

by the BIOS upon power-up, in order to comply with the board implementation.

MM - Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or

more modes of operation within the same function. These modes are associated with the same external (board) con-

nectivity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do

not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O

conﬁguration perspective. The mode selection method (registers and bits) as well as the signal speciﬁcation in each

mode, are described within the functional description of the relevant functional block.

Table 2. SIgnal/Pin Directory

Table 1. Buffer Types

Symbol

Description

INC

Input, CMOS compatible

INPCI

Input, PCI 3.3V

INSM

Input, SMBus compatible

INSTRP

Input, Strap pin with weak pull-down during strap time

INT

Input, TTL compatible

INTS

Input, TTL compatible with Schmidt Trigger

INULR

Input, with serial UL Resistor

OPCI

Output, PCI 3.3V

Op/n

Output, push-pull buffer that is capable of sourcing

p mA and sinking n mA

ODn

Output, open-drain output buffer that is capable of sinking

n mA

PWR

Power pin

GND

Ground pin

Signal

Pin(s)

Functional Group

DC Characteristics

MUX

Name

Section

Buffer Type

Section

ACK

Parallel Port

1.4.11

INT

10.2.5

AFD_DSTRB

Parallel Port

1.4.11

OD14, O14/14

10.2.9, 10.2.8

ASTRB

See SLIN_ASTRB

BADDR

101

Strap Conﬁguration

1.4.15

INSTRP

10.2.4

MUX

BOUT1

See DTR1_BOUT1

BOUT2

See DTR2_BOUT2

BUSY_WAIT

Parallel Port

1.4.11

INT

10.2.5

CHASI

Protection

1.4.13

INC

10.2.1

CHASO

Protection

1.4.13

OD6

10.2.9

MUX

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