SC16C752B datasheet(30/47 Pages) PHILIPS

No. de pieza	SC16C752B

Descripción Electrónicos	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

PDF	47 Pages

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Fabricante Electrónico	PHILIPS [NXP Semiconductors]

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30 / 47 page

Philips Semiconductors

SC16C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Product data

Rev. 03 — 14 December 2004

30 of 47

9397 750 14443

7.14 FIFO ready register

The FIFO ready register provides real-time status of the transmit and receive FIFOs

of both channels.

The FIFO Rdy register is a read-only register that can be accessed when any of the

two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and

loop-back is disabled. The address is 111.

Table 22:

FIFO Ready Register bits description

Bit

Symbol

Description

7:6

FIFO Rdy[7:6]

Unused; always 0.

FIFO Rdy[5]

RX FIFO B status. Related to DMA.

FIFO Rdy[4]

RX FIFO A status. Related to DMA.

3:2

FIFO Rdy[3:2]

Unused; always 0.

FIFO Rdy[1]

TX FIFO B status. Related to DMA.

FIFO Rdy[0]

TX FIFO A status. Related to DMA.

SC16C752B Datasheet(PDF) 30 Page - NXP Semiconductors