© VITESSE SEMICONDUCTOR CORPORATION

Page 7

1/17/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

10-bit Transceiver for Fibre

Channel and Gigabit Ethernet

Advance Product Information

VSC7133

G52187-0 Rev. 2.4

Figure 5: Receive Timing Waveforms

Table 3: Receive AC Characteristics

Parameters

Description

Min.

Max.

Units

Conditions

TTL Outputs Valid prior

to RCLK/RCLKN rise

4.0

3.0

—

—

ns

@ 1.0625Gb/s

@ 1.25Gb/s

TTL Outputs Valid after

RCLK or RCLKN rise

3.0

2.0

—

—

ns

@ 1.0625Gb/s

@ 1.25Gb/s

Delay between rising

edge of RCLK to rising

edge of RCLKN

-500

+500

ps

incoming data on Rx.

Period of RCLK and

RCLKN

1.98 x

2.02 x

ps

Whether or not locked to

serial data.

R(0:9), COMDET,

SIGDET, RCLK and

RCLKN rise and fall time

—2.4

ns

Latency from RX to

R(0:9)

12 bc + 1 ns

13 bc + 9 ns

bc

ns

bc = Bit clock

ns = Nano second

Data acquisition lock time

—1400

bc

8B/10B IDLE pattern.

bc= bit clocks

* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3

RCLK

R(0:9)

RCLKN

Data Valid

Data Valid

Data Valid