Pinout Description

(See Connection Diagram)

Pin 1, BOOTSTRAP 1 Input: Bootstrap capacitor pin for half

H-Bridge number 1. The recommended capacitor (10 nF) is

connected between pins 1 and 2.

Pin 2, OUTPUT 1: Half H-Bridge number 1 output.

Pin 3, DIRECTION Input: See

Table 1. This input controls

the direction of current flow between OUTPUT 1 and OUT-

PUT 2 (pins 2 and 10) and, therefore, the direction of rotation

of a motor load.

Pin 4, BRAKE Input: See

Table 1. This input is used to

brake a motor by effectively shorting its terminals. When

braking is desired, this input is taken to a logic high level and

it is also necessary to apply logic high to PWM input, pin 5.

The drivers that short the motor are determined by the logic

level at the DIRECTION input (Pin 3): with Pin 3 logic high,

both current sourcing output transistors are ON; with Pin 3

logic low, both current sinking output transistors are ON. All

output transistors can be turned OFF by applying a logic high

to Pin 4 and a logic low to PWM input Pin 5; in this case only

a small bias current (approximately −1.5 mA) exists at each

output pin.

Pin 5, PWM Input: See

Table 1. How this input (and DIREC-

TION input, Pin 3) is used is determined by the format of the

PWM Signal.

Pin 6, V

Pin 7, POWER GROUND/SENSE Connection: This pin is

the ground return for the power DMOS transistors of the

H-Bridge. The current through the H-Bridge can be sensed

by adding a small, 0.1

Ω, sense resistor from this pin to the

power supply ground.

Pin 8, SIGNAL GROUND: This is the ground return for the

internal logic circuitry used to control the PWM switching of

the H-Bridge.

Pin 9, THERMAL FLAG Output: This pin provides the ther-

mal warning flag output signal. Pin 9 becomes active-low at

145˚C (junction temperature). However the chip will not shut

itself down until 170˚C is reached at the junction.

Pin 10, OUTPUT 2: Half H-Bridge number 2 output.

Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for

half H-Bridge number 2. The recommended capacitor

(10 nF) is connected between pins 10 and 11.

TABLE 1. Logic Truth Table

PWM

Dir

Brake

Active Output Drivers

H

H

L

Source 1, Sink 2

H

L

L

Sink 1, Source 2

L

X

L

Source 1, Source 2

H

H

H

Source 1, Source 2

H

L

H

Sink 1, Sink 2

L

X

H

NONE

Application Information

TYPES OF PWM SIGNALS

The LMD18201 readily interfaces with different forms of

PWM signals. Use of the part with two of the more popular

forms of PWM is described in the following paragraphs.

Simple, locked anti-phase PWM consists of a single, vari-

able duty-cycle signal in which is encoded both direction and

amplitude information (see

Figure 2).A50% duty-cycle

PWM signal represents zero drive, since the net value of

voltage (integrated over one period) delivered to the load is

zero. For the LMD18201, the PWM signal drives the direc-

tion input (pin 3) and the PWM input (pin 5) is tied to logic

high.

Sign/magnitude PWM consists of separate direction (sign)

and amplitude (magnitude) signals (see

Figure 3). The (ab-

solute) magnitude signal is duty-cycle modulated, and the

absence of a pulse signal (a continuous logic low level) rep-

resents zero drive. Current delivered to the load is propor-

tional to pulse width. For the LMD18201, the DIRECTION in-

put (pin 3) is driven by the sign signal and the PWM input

(pin 5) is driven by the magnitude signal.

USING THE THERMAL WARNING FLAG

The THERMAL FLAG output (pin 9) is an open collector tran-

sistor. This permits a wired OR connection of thermal warn-

ing flag outputs from multiple LMD18201’s, and allows the

user to set the logic high level of the output signal swing to

match system requirements. This output typically drives the

interrupt input of a system controller. The interrupt service

routine would then be designed to take appropriate steps,

such as reducing load currents or initiating an orderly system

shutdown. The maximum voltage compliance on the flag pin

is 12V.

SUPPLY BYPASSING

During switching transitions the levels of fast current

changes experienced may cause troublesome voltage tran-

sients across system stray inductances.

It is normally necessary to bypass the supply rail with a high

quality capacitor(s) connected as close as possible to the V

S

Power Supply (Pin 6) and POWER GROUND (Pin 7). A 1 µF

high-frequency ceramic capacitor is recommended. Care

should be taken to limit the transients on the supply pin be-

low the Absolute Maximum Rating of the device. When oper-

ating the chip at supply voltages above 40V a voltage sup-

pressor (transorb) such as P6KE62A is recommended from

DS010793-4

FIGURE 2. Locked Anti-Phase PWM Control

DS010793-5

FIGURE 3. Sign/Magnitude PWM Control

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