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Timing Diagrams

Diagram 1: Divide by 6 Color Mode Sample and Data Output Timing

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

GH

GL

BL

BH

RH

RL

GH

GL

BH

BL

H = d13-d6

L = d5-d0

ADC Clock

(internal)

N+1

N

N

N-1

RH

N-4

N-5

N-5

N-4

N-4

DOE (Register 0, Bit 4) = 0

Diagram 2: Divide by 6 Monochrome Mode Sample and Data Output Timing (Green Input shown)

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

XX

XX

XX

XX

GH

GL

XX

XX

XX

XX

H = d13-d6

L = d5-d0

ADC Clock

(internal)

N

N-1

N+1

N

GH

N-4

DOE (Register 0, Bit 4) = 0

Diagram 3: Divide by 8 Color Mode Sample and Data Output Timing

VSMP

D7 -D0

Sample Signal

Sample Reference

MCLK

Level

Level

RH

RL

GL

GH

BH

BL

XX

XX

RH

RL

XX

H = d13-d6

L = d5-d0

ADC Clock

(internal)

N-1

N

N

N+1

GH

N-4

N-4

N-4

N-3

DOE (Register 0, Bit 4) = 0