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LM9627 Datasheet(PDF) 22 Page - National Semiconductor (TI) |
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LM9627 Datasheet(HTML) 22 Page - National Semiconductor (TI) |
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22 / 37 page ![]() Confidential 22 www.national.com Functional Description (continued) Figure 42. Example of Digital Video Port Timing in Progressive Scan Mode Figure 43. Example of Digital Video Port Timing in Interlaced Mode Figure 44. Example of Digital Video Port Timing in 2:1 Sub-sampling Mode Figure 45. Example of Digital Video Port Timing in 4:2 Sub-sampling Mode c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 pclk vsync hsync d[11:0] c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 frame 1 row1 row 2 row 1 row 2 frame 2 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable row delay c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 pclk vsync hsync d[11:0] c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 Odd Field row1 row 3 row 2 row 4 Even Field Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable row delay c0 c2 c4 c6 c8 c0 c2 c4 c6 c8 pclk vsync hysync d[11:0] c0 c2 c4 c6 c8 c0 c2 c4 c6 c8 row 3 frame 1 frame 2 row 1 row 3 row 1 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable inter-row delay c0 c2 c4 c6 c8 c0 c2 c4 c5 c8 pclk vsync hsync d[11:0] c0 c2 c4 c6 c8 c0 c2 c4 c6 c8 row 2 frame 1 frame 2 row 1 row 2 row 1 Programmable hsync to 1st valid pixel delay Programmable inter-frame delay Programmable inter-row delay |
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