WM8955 datasheet(11/43 Pages) WOLFSON

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WM8955L

Product Preview Rev 0.4 May2003

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA =+25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

tMCLKL

MCLK System clock pulse width low

tMCLKH

MCLK System clock cycle time

tMCLKY

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

DACLRC

(Output)

DACDAT

DST

DHT

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DBVDD = 3.3V, DGND = 0V, TA =+25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

DACLRC propagation delayfrom BCLK falling edge

tDL

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

DACLRC

BCH

BCL

BCY

DACDAT

LRSU

LRH

Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)

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