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AD7403

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER REQUIREMENTS

VDD1

4.5

5.5

VDD2

5.5

IDD1

VDD1 = 5.5 V

IDD2

VDD2 = 5.5 V

VDD2 = 3.3 V

Power Dissipation

231

297

VDD1 = VDD2 = 5.5 V

185

231

VDD1 = 5.5 V, VDD2 = 3.3 V

For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%.

See the Terminology section.

Not production tested. Sample tested during initial release to ensure compliance.

AD7403-8

VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +105°C, fMCLKIN1 = 5 MHz to 20 MHz,

tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective

ground.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

Bits

Filter output truncated to 16 bits

Integral Nonlinearity (INL)2

±2

±6.5

LSB

Differential Nonlinearity (DNL)2

±0.99

LSB

Guaranteed no missed codes to 16 bits

Offset Error2

±1

±1.7

Offset Drift vs. Temperature3

6.8

µV/°C

Offset Drift vs. VDD13

425

µV/V

Gain Error2

±0.2

±0.8

% FSR

fMCLKIN = 16 MHz

±0.2

±1.4

% FSR

fMCLKIN = 20 MHz

Gain Error Drift vs. Temperature3

ppm/°C

µV/°C

Gain Error Drift vs. VDD13

±0.2

mV/V

ANALOG INPUT

Input Voltage Range

−320

+320

Full-scale range

−250

+250

For specified performance

Input Common-Mode Voltage Range

−200 to +300

Dynamic Input Current

±45

±50

µA

VIN+ = ±250 mV, VIN− = 0 V

0.05

µA

VIN+ = 0 V, VIN− = 0 V

DC Leakage Current

±0.01

±0.6

µA

Input Capacitance

DYNAMIC SPECIFICATIONS

VIN+ = 1 kHz

Signal-to-Noise-and-Distortion Ratio (SINAD)2

Signal-to-Noise Ratio (SNR)2

Total Harmonic Distortion (THD)2

−94

Peak Harmonic or Spurious Noise (SFDR)2

−94

Effective Number of Bits (ENOB)2

13.3

14.2

Bits

ISOLATION TRANSIENT IMMUNITY2

kV/µs

LOGIC INPUTS

CMOS with Schmitt trigger

Input High Voltage (VIH)

0.8 × VDD2

Input Low Voltage (VIL)

0.2 × VDD2

Input Current (IIN)

±0.6

µA

Input Capacitance (CIN)

LOGIC OUTPUTS

Output High Voltage (VOH)

VDD2 − 0.1

IO = −200 µA

Output Low Voltage (VOL)

0.4

IO = +200 µA

Rev. B | Page 4 of 24

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