| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
WM8756 Datasheet(PDF) 10 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8756 Datasheet(HTML) 10 Page - Wolfson Microelectronics plc |
|
10 / 39 page ![]() WM8756 Advance Information AI Rev 1.3 October 2001 10 DSD AUDIO BIPHASE INTERFACE DSDCLK128 DSD[0:5] t BDCH t BDCY128 t BDS D(n) inverse D(n) t BDH DSDCLK64 inverse D(n-1) t DIFF t BDCL t BDCY64 Figure 4 DSD Audio Data Timing - Phase Modulation Mode Test Conditions AVDD= DVDD = 5V, AGND= GR= DGND = 0V, TA = +25 oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information DSDCLK64 cycle time tBDCY64 354.4 ns DSDCLK128 cycle time tBDCY128 177.2 ns DSDCLK128 pulse width high tBDCH 80 ns DSDCLK128 pulse width low tBDCL 80 ns DSD[0:5] set-up time to DSDCLK128 rising edge tBDS 10 ns DSD[0:5] hold time from DSDCLK128 rising edge tBDH 10 ns Difference in edge timing of DSDCLK64 to DSDCLK128 tDIFF 20 ns Table 9 DSD Digital Audio Timing |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |