DSP56156ROM datasheet(69/76 Pages) MOTOROLA

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Design Considerations

DSP56156 Data Sheet

MOTOROLA

DSP Programming

Considerations

1. Synchronization of Status Bits

from Host to DSP

DMA, HF1, HF0, and HCP, HTDE,

and HRDF status bits are set or

cleared by the host processor side of

the interface. These bits are individ-

ually synchronized to the DSP clock.

(Refer to the DSP56156 User’s Manual,

I/O Interface section, Host/DMA In-

terface Programming Model for de-

scriptions of these status bits.)

2. Reading HF0 and HF1 as an

Encoded Pair

Care must be exercised when reading

status bits HF0 and HF1 as an encod-

ed pair, i.e., the four combinations 00,

01, 10, and 11 each have significance.

A very small probability exists that

the DSP will read the status bits syn-

chronized during transition. There-

fore, HF0 and HF1 should be read

twice and checked for consensus.

Bus Operation

Figure 43 depicts the operation of the external memory interface with multiple wait states.

Figure 43 Read and Write Bus Operation (3 Wait States)

T2 Tw T2

T2 Tw

Data out

CLKO

A0-A15

PS/DS

R/W

D0-D15

Data in

DSP Programming Considerations

Bus Operation

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56156ROM Datasheet(PDF) 69 Page - Motorola, Inc

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