USB2517 datasheet(15/58 Pages) MICROCHIP

15 / 58 page

 2013-2016 Microchip Technology Inc.

DS00001598B-page 15

USB2517/USB2517I

TEST

IPD

TEST pin

XNOR continuity tests all signal pins on the hub. Please contact

your MCHP representative for a detailed description of how this

test mode is enabled and utilized.

Power, Ground, No Connect

VDD18

VDD Core

+1.8V core power. This pin must have a 1.0

F (or greater) ±20%

(ESR <0.1

) capacitor to VSS.

VDD33PLL

VDD 3.3 PLL Regulator Reference

+3.3V power supply for the Digital I/O. If the internal PLL 1.8V reg-

ulator is enabled, then this pin acts as the regulator input.

VDD18PLL

VDD PLL

+1.8V Filtered analog power for internal PLL. This pin must have a

1.0

F (or greater) ±20% (ESR <0.1) capacitor to VSS.

VDD33

VDD I/O

+3.3V Digital I/O power

VDDA33

VDD Analog I/O

+3.3V Filtered analog PHY power which is shared between adja-

cent ports.

VDD33CR

VDDIO/VDD 3.3 Core Regulator Reference

+3.3V power supply for the Digital I/O. If the internal core regulator

is enabled, then VDD33CR acts as the regulator input.

Ground

VSS

Slug

Ground

TABLE 5-2:

USB2517I SMBUS OR EEPROM INTERFACE BEHAVIOR

CFG_SEL2

CFG_SEL1

CFG_SEL0

SMBus or EEPROM Interface Behavior

Internal Default Configuration

• Strap Option sare Enabled

Configured as an SMBus slave for external download of

user-defined descriptors

• SMBus slave address is ‘0101100’

• Strap Options are Disabled

• All Settings are Controlled by Registers

Internal Default Configuration

• Strap Options are Enabled

• Bus Power Operation

• LED Mode = USB

TABLE 5-1:

USB2517/USB2517I PIN DESCRIPTIONS (CONTINUED)

Symbol

64 QFN

Buffer Type

Description

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