AS4SD16M16 datasheet(20/52 Pages) MICROSS

20 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another bank

while an access command with auto precharge enabled is

executing is not allowed by SDRAMs, unless the SDRAM

supports CONCURRENT AUTO PRECHARGE. Micross

SDRAMs support CONCURRENT AUTO PRECHARGE.

Four cases where CONCURRENT AUTO PRECHARGE oc-

curs are defined below.

READ with Auto Precharge

1. Interrupted by a READ (with or without auto precharge);

A READ to bank m will interrupt a READ on bank n, CAS

latency later. The PRECHARGE to bank n will begin when

the READ to bank m is registered (Figure 24).

2. Interrupted by a WRITE (with or without auto precharge):

A WRITE to bank m will interrupt a READ on bank n when

registered. DQM should be used two clocks prior to the WRITE

command to prevent bus contention. The PRECHARGE to

bank n will begin when the WRITE to bank m is registered

(Figure 25).

FIGURE 24: READ With Auto Precharge Interrupted by a READ

FIGURE 25: READ With Auto Precharge Interrupted by a WRITE

AS4SD16M16 Datasheet(PDF) 20 Page - Micross Components