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LIS3MDL Datasheet(PDF) 14 Page - STMicroelectronics |
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LIS3MDL Datasheet(HTML) 14 Page - STMicroelectronics |
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14 / 33 page ![]() Application hints LIS3MDL 14/33 DocID024204 Rev 4 4 Application hints Figure 5. LIS3MDL electrical connections 4.1 External capacitors The LIS3MDL requires one external capacitor (C1 = 100 nF) connected between pin 4 and GND. The device core power supply line (Vdd) needs one high-frequency decoupling capacitor (C3 = 100 nF, ceramic) as near as possible to the supply pin, and a low-frequency electrolytic capacitor (C2 = 1 μF). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). The functionality of the device and the measured magnetic field data is selectable and accessible through the I2C / SPI interfaces. The functions, the threshold and the timing of the interrupt pin (INT) can be completely programmed by the user through the I2C / SPI interfaces. When I2C or 3-wire SPI is used, the SDO/SA1 pin must be connected to Vdd_IO or GND. 4.2 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com. Vdd C 3 =100 nF GND C 2 =1 µF 4 1 55 77 11 12 Vdd_IO CS C 1 =100 nF (TOP VIEW) 10 SDO/SA1 DRDY 8 INT 6 9 2 3 TOP VIEW DIRECTION OF DETECTABLE MAGNETIC FIELDS X Z Y |
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