| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
S-34C02B Datasheet(PDF) 7 Page - Seiko Instruments Inc |
|
|
|||||||||||||||||||||||||||||
S-34C02B Datasheet(HTML) 7 Page - Seiko Instruments Inc |
|
7 / 26 page ![]() 2-WIRE SERIAL E2PROM FOR DIMM SERIAL PRESENCE DETECT Rev.1.0_02_U S-34C02B 7 Pin Functions 1. VCC (Power supply) pin The VCC pin is used to apply positive supply voltage. Regarding the applied voltage value, refer to " Recommended Operating Conditions ". Set a bypass capacitor of about 0.1 μF between the VCC pin and the GND pin to make the power supply voltage stable. 2. A0, A1 and A2 (Slave address input) pins In this IC, to set the slave address, connect each of A0 pin, A1 pin and A2 pin to the GND pin or the VCC pin. Therefore the users can set 8 types of slave address by a combination of A0, A1, A2 pins. Comparing the slave address transmitted from the master device and one that you set, makes possible to select one slave address from other devices connected onto the bus. Each of A0 pin, A1 pin and A2 pin has a built-in pull-down resistor. In open, the pin is set to the same status as it connected to the GND pin. 3. SDA (Serial data I/O) pin The SDA pin is used for the bi-directional transmission of serial data. This pin is a signal input pin, and an Nch open-drain output pin. In use, generally, connect the SDA line to any other device which has the open-drain or open-collector output with Wired-OR connection by pulling up to VCC by a resistor. Figure 4 shows the relation with an output load. 4. SCL (Serial clock input) pin The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. 5. WP (Write protect input) pin When hardware write protect is used, connect the WP pin to VCC. When hardware write protect is not used, be sure to leave the WP pin open or connect it to the GND pin. When software write protect is used, it inhibits write in 50% of the lower address (addresses 00h to 7Fh) in all memory area according to the status of the protect register when the WP pin is left open or connected to the GND pin. Value of load capacity [pF] 100 10 0 2 4 6 8 fSCL = 400 kHz Maximum value of pull-up resistor [k Ω] 10 12 14 16 18 20 Figure 4 Output Load |
|
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |