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AT91SAM7A1-AI Datasheet(PDF) 6 Page - ATMEL Corporation

No. de pieza AT91SAM7A1-AI
Descripción Electrónicos  ARM7TDMI BASED MICROCONTROLLER
PDF  14 Pages
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Fabricante Electrónico  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT91SAM7A1-AI Datasheet(HTML) 6 Page - ATMEL Corporation

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PRELIMINARY
AT91SAM7A1 Summary
6048AS–ATARM–07/04
Notes:
1. Values in brackets are values at reset H (high level), L (low level), Z (tri-state), I (input), O (output).
2. The EBI bus (address bus A[21:0], data bus D[15:0] and control lines NOE/NRD, NWR0/NWE, NWR1/NUB and NCS[3:0]) is
tri-stated when NRESET is at a logical 0. This allows external equipment to access the external memory devices (e.g., for
Flash programming). It is up to the application to add an external pull-up on the chip select lines in order to avoid EBI con-
flicts at reset.
3. The EBI data bus D[15:0] has an internal pull-down.
Timer T0
T0TIOA[2:0]/MPIO
Capture/waveform I/O
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
T0TIOB[2:0]/MPIO
Trigger/waveform I/O
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
T0TCLK[2:0]/MPIO
External clock/trigger/input
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
ADC
ANAIN[7:0]
Analog input
I
VREFP
Positive voltage reference
I
SPI
SPCK/MPIO
SPI clock line
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
MISO/MPIO
SPI master in slave out
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
MOSI/MPIO
SPI master out slave in
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
NPCS[3:1]/MPIO
SPI chip select
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
NPCS0/MPIO
SPI chip select
I/O (I)
(Z)
Multiplexed with a general-purpose I/O
CAN0
CANRX0
CAN0 receive line
I
L
CANTX0
CAN0 transmit line
O
L (H)
JTAG
SCANEN
Scan enable (Factory test)
I
H
Internal pull-down (must be connected
to GND or leave unconnected for
normal operation)
TDI
Test Data In
I
Schmitt trigger, internal pull-up
TDO
Test Data Out
O
TMS
Test Mode Select
I
Schmitt trigger, internal pull-up
TCK
Test Clock
I
Schmitt trigger, internal pull-up
TEST
Factory test
I
H
Internal pull-down (must be connected
to GND or leave unconnected for
normal operation)
Power
Supplies
VDDCORE
Core Power Supply
–
3.3V
VDDANA
Analog Power Supply
–
3.3V
VDDIO
I/O Lines Power Supply
–
3.3V to 5V
GND
Ground
–
Table 2. Pin Description
Module
Name
Function
Type
(1)
Level
(1)
Comments



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