ST72774 datasheet(108/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

Slave Receiver

Following the address reception and after SR1

from the SDA line into the DR register via the

internal shift register. After each byte, the following

events occur in sequence:

– Acknowledge pulse is generated if the ACK bit is

set.

– EVF and BTF bits are set.

– An interrupt is generated if the ITE bit is set.

Then the interface waits for a read of the SR1

holding the SCL line low (see Figure 67 Transfer

sequencing EV2).

Slave Transmitter

Following the address reception and after SR1

the DR register to the SDA line via the internal shift

The slave waits for a read of the SR1 register

followed by a write in the DR register, holding the

SCL line low (see Figure 67 Transfer sequencing

EV3).

When the acknowledge pulse is received:

– EVF and BTF bits are set.

– An interrupt is generated if the ITE bit is set.

Closing slave communication

After the last data byte is transferred, a Stop

Condition is generated by the master. The

interface detects this condition and in this case:

– EVF and STOPF bits are set.

– An interrupt is generated if the ITE bit is set.

Then the interface waits for a read of the SR2

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

the BERR bits are set and an interrupt is gener-

ated if the ITE bit is set.

If it is a Stop then the interface discards the data,

releases the lines and waits for another Start

condition.

If it is a Start then the interface discards the data

and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set and an inter-

rupt is generated if the ITE bit is set.

Note:In both cases, SCL line is not held low; however,

SDA line can remain low due to possible «0» bits

transmitted last. It is then necessary to release both

lines by software.

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

Other Events

ADSL: Detection of a Start condition after an

acknowledge time-slot.

The state machine is reset and starts a new

process. The ADSL bit is set and an interrupt is

generated if the ITE bit is set. The SCL line is

stretched low.

STOPF: Detection of a Stop condition after an

acknowledge time-slot.

The state machine is reset. Then the STOPF

flag is set and an interrupt is generated if the ITE

bit is set.

ST72774 Datasheet(PDF) 108 Page - STMicroelectronics

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