ST72774 datasheet(107/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

4.8.5.2 DDC/CI - Factory Alignment Interface

4.8.5.2.1 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

4.8.6. for the bit definitions.

The DDC/CI interface works as an I/O interface

between the microcontroller and the DDC2Bi,

EDDC or Factory alignment protocols. It receives

and transmits data in Slave I2C mode using an

interrupt or polled handshaking.

The interface is connected to the I2C bus by a data

pin (SDAD) and a clock pin (SCLD) configured as

open drain.

The DDC/CI interface has five internal register

locations.

Two of them are used for initialization of the

interface:

– Own Address Register OAR

– Control register CR

The following four registers are used during data

transmission/reception:

– Data Register DR

– Control Register CR

– Status Register 1 SR1

– Status Register 2 SR2

The interface decodes an I2C or DDC2Bi address

stored by software in the OAR register and/or the

EDDC address (60h/61h) as its default hardware

address.

After a reset, the interface is disabled.

4.8.5.2.2 I2C Modes

General description

In I2C mode, the interface can operate in the

following modes:

– Slave transmitter/receiver

Both start and stop conditions are generated by

the master. The I2C clock (SCL) is always

received by the interface from a master, but the

interface is able to stretch the clock line.

The interface is capable of recognizing both its

own programmable address (7-bit) and its default

hardware address (Enhanced DDC address: 60h/

61h). The Enhanced DDC address detection may

be enabled or disabled by software. It never

recognizes the Start byte (01h) whatever its own

address is.

Slave Mode

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register; then it is compared with the

programmable address of the interface or the

Enhanced DDC address (if selected by software).

Address not matched: the interface ignores it

and waits for another Start condition.

Address matched: the following events occur in

sequence:

– Acknowledge pulse is generated if the ACK bit is

set.

– EVF and ADSL bits are set.

– An interrupt is generated if the ITE bit is set.

Then the interface waits for a read of the SR1

Transfer sequencing EV1).

Next, the DR register must be read to determine

from the least significant bit if the slave must enter

Receiver or Transmitter mode.

ST72774 Datasheet(PDF) 107 Page - STMicroelectronics

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