CS8415A-CS datasheet(16/42 Pages) CIRRUS

16 / 42 page

CS8415A

routed to both the left and right data fields on SD-

OUT. Similarly, sub-frame B data will be routed to

both the left and right data fields of the next word

clock cycle of SDOUT.

Using mono mode is only necessary if the serial

audio output port must run at 96 kHz. If the

CS8415A is kept in normal stereo mode, and re-

ceives AES3 data arranged in mono mode, then

the serial audio output port will run at 48 kHz, with

left and right data fields representing consecutive

audio samples.

RCBL

Out

VLRCK

C, U

Ouput

RCBL and C output are only available in hardware mode.

RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.

VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.

VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.

If the serial audio output port is in master mode, VLRCK = OLRCK.

If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.

C, U transitions are aligned within 1% of VLRCK period to VLRCK edges

Figure 7. AES3 Receiver Timing for C & U pin output data

CS8415A-CS Datasheet(PDF) 16 Page - Cirrus Logic