UT621024LS-55LL datasheet(4/12 Pages) ETC

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UTRON

UT621024

Rev. 1.5

128K X 8 BIT LOW POWER CMOS SRAM

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80036

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919



TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

DOUT

Data Valid

tAA

tOH

READ CYCLE 2 (

CE , CE2 and OE Controlled) (1,3,5,6)

Notes :

WE is HIGH for read cycle.

2. Device is continuously selected

CE =VIL and CE2=VIH.

3. Address must be valid prior to or coincident with

CE and CE2 transition; otherwise tAA is the limiting parameter.

OE is low.

5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.

6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.

tRC

tAA

tACE1

tACE2

tOE

tOLZ

tCLZ1

tCLZ2

High-Z

tCHZ1

tCHZ2 t

OHZ

tOH

Data Valid

High-Z

Address

CE2

DOUT

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