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MT9072AB Datasheet(PDF) 117 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 117 Page - Zarlink Semiconductor Inc |
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117 / 275 page ![]() MT9072 Data Sheet 117 Zarlink Semiconductor Inc. 2MFREFR (0) MultiFrame Reframe. Only applicable in D4 mode. Setting this bit causes an automatic multiframe reframe. The signaling bits are frozen until multiframe synchronization is achieved. Terminal frame synchronization is not affected. 1JTS (0) Japan Telecom Synchronization. If this bit is set, the S-bit is included in the CRC6 calculation for the ESF framing Mode. 0 TxSYNC (0) Transmit Synchronization. Setting this bit causes the transmit multiframe boundary to be internally synchronized to the incoming S-bits on DSTi channel 31 bit 0. Bit Name Functional Description Table 63 - Framing Mode Select (R/W Address Y00) (T1) |
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