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MT9072AB Datasheet(PDF) 46 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 46 Page - Zarlink Semiconductor Inc |
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46 / 275 page  MT9072 Data Sheet 46 Zarlink Semiconductor Inc. 5.1.1 T1 D4 Framing For D4 links the S-bit position contains an alternating 101010... pattern inserted into every second S-bit. These bits are intended for determination of frame boundaries, and they are referred to as Ft bits. A separate fixed pattern, repeating every superframe, is interleaved with the Ft bits. This fixed pattern (001110) is used to delineate the 12 frame superframe. These bits are referred to as the Fs bits. In D4 frames # 6 and #12, the LSB of each channel byte may be replaced with A bit (frame #6) and B bit (frame #12) signaling information. See Table 8. 5.1.2 T1 ESF Framing For ESF links the 6 bit framing pattern 001011, inserted into every 4th S-bit position, is used to delineate both frame and superframe boundaries. Frames #6, 12, 18 and 24 may contain the A, B, C and D signaling bits, respectively. A 4 kHz data link is embedded in the S-bit position, interleaved between the framing pattern sequence (FPS) and the transmit CRC-6 remainder (from the calculation done on the previous superframe). See Table 9. Frame # Ft Fs Signaling 11 20 30 40 51 61 A 70 81 91 10 1 11 0 12 0 B Table 8 - D4 Superframe Structure (T1) Frame # FPS FDL CRC Signaling 1X 2CB1 3X 40 5X 6CB2 A 7X Table 9 - ESF Superframe Structure (T1) |
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