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TMS570LS Datasheet(PDF) 95 Page - Texas Instruments |
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TMS570LS Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 107 page  t(DMM)dsu t(DMM)dho DMMSYNC DMMCLK DMMDATA t(DMM)sho t(DMM)ssu t(DMM)cyc tr tf t(DMM)h t(DMM)l TMS570LS20206-EP, TMS570LS20216-EP www.ti.com SPNS209A – JUNE 2012 – REVISED AUGUST 2012 7.17 DMM Timings 7.17.1 DMMCLK Timing Figure 7-24. DMMCLK Timing Table 7-25. DMMCLK Timing Parameter Minimum Description t(DMM)cyc tc(HCLK) * 2 Clock period t(DMM)h t(DMM)cyc/2-(tr+tf)/2 High pulse width t(DMM)l t(DMM)cyc/2-(tr+tf)/2 Low pulse width 7.17.2 DMMDATA Timing Figure 7-25. DMMDATA Timing Table 7-26. DMMDATA Timing Parameter Minimum Description t(DMM)ssu 2ns SYNC active to clk falling edge setup time t(DMM)sho 3ns clk falling edge to SYNC deactive hold time t(DMM)dsu 2ns DATA to clk falling edge setup time t(DMM)dho 3ns clk falling edge to DATA hold time Copyright © 2012, Texas Instruments Incorporated Peripheral and Electrical Specifications 95 Submit Documentation Feedback Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP |
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