PCK12429BD datasheet(7/14 Pages) PHILIPS

7 / 14 page

Philips Semiconductors

Product data

PCK12429

25–400 MHz differential PECL clock generator

2002 Jun 03

SW00730

N DIVIDE

(2, 4, 8, 16)

PLL 12429

SHIFT

REG

14-BIT

VCO_CLK

FREF

MCNT

FOUT

(VIA ENABLE GATE)

SEL_CLK

SCLOCK

SDATA

DECODE

LATCH

Reset

M COUNTER

SLOAD

PLOADB

FDIV4

MCNT

LOW

FOUT

MCNT

FREF

HIGH

TEST

MUX

TEST

• T2 = T1 = 1. T0 = 0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin.

PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.

Figure 2. Serial Test Clock Block Diagram

DC CHARACTERISTICS (Tamb = 0 to 70 °C, VCC = 3.3 V ± 5%)

SYMBOL

PARAMETER

CONDITION

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VIH

Input HIGH Voltage

VCC = 3.3 V

2.0

—

VIL

Input LOW Voltage

VCC = 3.3 V

—

0.8

IIN

Input Current

—

1.0

VOH

Output HIGH Voltage

TEST

IOH = –0.8 mA

2.5

—

VOL

Output LOW Voltage

TEST

IOL = 0.8 mA

—

0.4

Output HIGH Voltage

FOUT

VCC0 = 3.3 V

217

250

VOH

Output HIGH Voltage

FOUT

CC0

(Notes 1 and 2)

2.17

—

2.50

Output LOW Voltage

FOUT

VCC0 = 3.3 V

141

176

VOL

Output LOW Voltage

FOUT

CC0

(Notes 1 and 2)

1.41

—

1.76

ICC

Power Supply Current

VCC1

100

ICC

Power Supply Current

PLL_VCC

—

NOTES:

1. Output levels will vary 1:1 with VCC0 variation.

2. 50

Ω to VCC – 2.0 V pulldown.

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