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AD1835AS Datasheet(PDF) 21 Page - Analog Devices |
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AD1835AS Datasheet(HTML) 21 Page - Analog Devices |
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21 / 23 page ![]() REV. PrA PRELIMINARY TECHNICAL DATA AD1835 –21– CASCADE MODE Dual AD1835Cascade The AD1835 can be cascaded to an additional AD1835 that, in addition to six external stereo ADCs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade is designed to connect to a SHARC DSP and operates in a time division multiplexing (TDM) format. Figure 14 shows the connection diagram for cascade operation. The digital interface for both parts must be set to operate in Auxiliary 512 mode by programming ADC Control Register II. AD1835 #1 is set as a master device by connecting the M/S pin to DGND, and AD1835 #2 is set as a slave device by connecting the M/S to DVDD. Both devices should be run from the same MCLK and PD/RST signals to ensure that they are synchronized. With Device 1 set as a master, it will generate the frame-sync and bit clock signals. These signals are sent to the SHARC and Device 2 ensuring that both know when to send and receive data. The cascade can be thought of as two 256-bit shift registers, one for each device. At the beginning of a sample interval, the shift registers contain the ADC results from the previous sample interval. The first shift register (Device 1) clocks data into the SHARC and also clocks in data from the second shift register (Device 2). While this is happening, the SHARC is sending DAC data to the second shift register. By the end of the sample interval, all 512 bits of ADC data in the shift registers will have been clocked into the SHARC and been replaced by DAC data which is subsequently written to the DACs. Figure 15 shows the timing diagram for the cascade operation. AUX ADC (SLAVE) ALRCLK ABCLK ASDATA DSDATA ALRCLK ABCLK ASDATA DSDATA AD1835 #1 (MASTER) AD1835 #2 (SLAVE) SHARC (SLAVE) AUX ADC (SLAVE) AUX ADC (SLAVE) AUX ADC (SLAVE) AUX ADC (SLAVE) AUX ADC (SLAVE) DRx RFSx RCLKx TCLKx DTx TFSx Figure 14. Cascade AD1835 #1 DACs L1 L2 L3 L4 R1 R2 R3 R4 AD1835 #2 DACs L1 L2 L3 L4 R1 R2 R3 R4 TFSx/ RFSx DTx AD1835 #1 ADCs L1 L2 L3 L4 R1 R2 R3 R4 AD1835 #2 ADCs L1 L2 L3 L4 R1 R2 R3 R4 DRx 256 ABCLKs 256 ABCLKs MSB MSB-1 LSB 32 ABCLKs ABCLK DTx MSB MSB-1 LSB DRx DON’T CARE Figure 15. Cascade Timing |
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