AP0100CS datasheet(47/73 Pages) ONSEMI

No. de pieza	AP0100CS

Descripción Electrónicos	High-Dynamic Range (HDR) Image Signal Processor (ISP)

PDF	73 Pages

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Fabricante Electrónico	ONSEMI [ON Semiconductor]

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AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

Protocol

Sequential WRITE, Start at Random Location

This sequence (Figure 37) starts in the same way as the single WRITE to random location

(Figure 36). Instead of generating a no-acknowledge bit after the first byte of data has

been transferred, the master generates an acknowledge bit and continues to perform

byte writes until “L” bytes have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 37:

Sequential WRITE, Start at Random Location

Slave Address

A Reg Address[15:8]

Write Data

Reg Address[7:0]

Write Data

Previous Reg Address, N

Reg Address, M

M+1

M+2

M+1

M+3

Write Data

M+L-2

M+L-1

M+L

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

Write Data

(15:8)

Write Data

(7:0)

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