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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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CS98100 Datasheet(PDF) 13 Page - Cirrus Logic |
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CS98100 Datasheet(HTML) 13 Page - Cirrus Logic |
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13 / 60 page  CS98100 13 1.2.5 Digital Audio Interface Timing Figure 8 and Figure 9 illustrate the signal timing for the digital audio pins. The bi-directional AUD_XCK pin clocks at 8x the frequency of the AUD_BCK pin. The AUD_BCK pin outputs at 32x or 48x of the sample frequency, and transitions on the falling edge of the AUD_XCK pin. AUD_BCK is shown without polarity to indicate the polarity is programmable. Symbol Description Min Typ Max Unit tslri AIN_LRCK setup to AUD_BCK active edge 25 - ns tsdi AIN_DATA setup to AUD_BCK active edge 25 - ns thsdi AIN_DATA hold time after AUD_BCK active edge 1 - ns Table 5. Digital Audio In Characteristics Figure 8. Digital Audio In Timing Diagram *AUD_BCK (Output) AIN_DATA (Input) AIN_LRCK (Input) tlrts tsdsus tsdhs * Active clock edge is programmable. Timing is referenced from active edge. |
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