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PIFE32251B-R68MS Datasheet(PDF) 56 Page - Texas Instruments |
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PIFE32251B-R68MS Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 157 page  VDC VIN LDO5V VLDO5 LDO5V V5ADS3 PG_V5ADS3 EN5VSW VDC VREGVR2 VREGVR4 VIN5VSW VREGVR1 Copyright © 2016, Texas Instruments Incorporated VDC AGND EC VIN EN3V3SW LDO3V VOUT3V3SW VOUT3V3SW VLDO3 LDO3V N AGND AGND Copyright © 2016, Texas Instruments Incorporated 56 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated Figure 6-4. LDO3V and 3V3SW Load Switch 6.3.5 5-V LDO and 5VSW Load Switch The LDO5V powers up when Vin pin goes above the UVLO5V threshold. The LDO5V powers the gate drives for all the five VRs of the PMIC. The 5-V load switch is used to switch the gate drive source from the internal LDO5V LDO to the 3.3-V PWM VR output as soon as the 3.3-V VR powergood signal indicates it is good. This significantly improves the efficiency of the VRs whose effect is more significant at lower VR load current, and VR input voltage. The load switch is enabled by the EN5VSW pin. Connect the V5A_PG signal to the EN5VSW pin. When the EN5VSW pin is high, the LDO5V internal reference drops to 4.5 V to ensure the 5-V VR drives all the gate drive current, but also ensures the gate drive never falls below 4.5 V. When EN5VSW is low, the LDO resumes to 5-V internal reference and the load switch is turned off to disconnect the 5-V VR. Figure 6-5. 5-V LDO and 5VSW Load Switch |
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