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M38B53M4-059FP Datasheet(PDF) 232 Page - Mitsubishi Electric Semiconductor |
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M38B53M4-059FP Datasheet(HTML) 232 Page - Mitsubishi Electric Semiconductor |
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232 / 355 page ![]() 2-144 38B5 Group User’s Manual APPLICATION 2.8 Watchdog timer Fig. 2.8.2 Structure of watchdog timer control register 2.8 Watchdog timer The watchdog timer is a 20-bit down-count counter consisting of a low-order 8 bits and a high-order 12 bits. “1” is subtracted from the watchdog timer each time a count source inputs. This paragraph describes the setting method of watchdog timer relevant register, notes etc. 2.8.1 Memory assignment Fig. 2.8.1 Memory assignment of watchdog timer relevant register 2.8.2 Relevant register The watchdog timer starts counting by writing an arbitrary value to the watchdog timer control register. Figure 2.8.2 shows the structure of the watchdog timer control register. Watchdog timer contort register (WDTCON) 002B16 Address Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON: address 2B16) b 0 1 2 3 4 5 6 1 Functions Name At reset R W 1 1 1 1 1 0 Watchdog timer H (high-order 6 bits of reading exclusive) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled 7 0 Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 |
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