SI5341_16 datasheet(27/53 Pages) SILABS

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Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Jitter Generation Locked to Ex-

ternal Clock3

JGEN

Integer Mode4

12 kHz to 20 MHz

—

140

180

fs rms

Fractional/DCO Mode5

12 kHz to 20 MHz

—

160

210

fs rms

JPER

Derived from integrated

phase noise

—

110

—

fs pk-pk

JCC

—

180

—

fs pk

JPER

N = 10,000 cycles Integer

or Fractional Mode4, 5 .

Measured in the time do-

main. Performance is limi-

ted by the noise floor of

the equipment.

—

7400

—

fs pk-pk

JCC

—

6700

—

fs pk

Jitter Generation Locked to Ex-

ternal XTAL

XTAL Frequency = 48 MHz

JGEN

Integer Mode4

12 kHz to 20 MHz

—

140

fs rms

Fractional/DCO Mode5

12 kHz to 20 MHz

—

115

170

fs rms

JPER

Derived from integrated

phase noise

—

110

—

fs pk-pk

JCC

—

180

—

fs pk

JPER

N = 10, 000 cycles Integer

or Fractional Mode.4, 5

Measured in the time do-

main. Performance is limi-

ted by the noise floor of

the equipment.

—

7400

—

fs pk-pk

JCC

—

6600

—

fs pk

XTAL Frequency = 25 MHz

JGEN

Integer Mode4

12 kHz to 20 MHz

115

140

fs rms

Fractional Mode5

12 kHz to 20 MHz

140

190

fs rms

Notes:

1. PLL lock time is measured by first letting the PLL lock, then turning off the input clock, and then turning on the input clock. The

time from the first edge of the input clock being re-applied until LOL de-asserts is the PLL lock time.

2. Measured as time from valid VDD and VDD33 rails (90% of their value) to when the serial interface is ready to respond to com-

mands. Measured in SPI 4-wire mode, with SCLK @ 10 MHz.

3. Jitter generation test conditions fIN = 100 MHz, fOUT = 156.25 MHz LVPECL.

4. Integer mode assumes that the output dividers (Nn/Nd) are configured with an integer value.

5. Fractional and DCO modes assume that the output dividers (Nn/Nd) are configured with a fractional value and the feedback divid-

er is integer.

Si5341/40 Rev D Data Sheet

Electrical Specifications

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