84021AY

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 7, 2003

2

Integrated

Circuit

Systems, Inc.

ICS84021

M divider and N output divider to a specific default state that will

automatically occur during power-up. The TEST output is LOW

when operating in the parallel input mode. The relationship be-

tween the VCO frequency, the crystal frequency and the M di-

vider is defined as follows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock for a

25MHz reference are defined as 25

≤ M ≤ 31. The frequency

out is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and

S_LOAD is LOW. The shift register is loaded by sampling

the S_DATA bits with the rising edge of S_CLOCK. The con-

tents of the shift register are loaded into the M divider and N

output divider when S_LOAD transitions from LOW-to-HIGH.

The M divide and N output divide values are latched on the

HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,

data at the S_DATA input is passed directly to the M divider

and N output divider on each rising edge of S_CLOCK. The

serial mode can be used to program the M and N bits and

test bits T1 and T0. The internal registers T0 and T1 deter-

mine the state of the TEST output as follows:

fVCO = fxtal x M

T1

T0

TEST Output

00

LOW

0

1

S_DATA, Shift Register Input

1

0

Output of M divider

1

1

CMOS Fout

*NOTE: The NULL timing slot must be observed.

Time

M, N

t

S

t

H

t

S

t

H

t

S

T1

T0

*NULL

N1

N0

M8

M7

M6

M5

M4

M3

M2

M1

M 0

FOUT = fVCO = fxtal x M

N

N

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

NOTE: The functional description that follows describes op-

eration using a 25MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the

Input Frequency Characteristics, Table 5, NOTE 1.

The ICS84021 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A fundamental crystal is used as the input to the on-

chip oscillator. The output of the oscillator is fed into the phase

detector. A 25MHz crystal provides a 25MHz phase detector

reference frequency. The VCO of the PLL operates over a

range of 620MHz to 780MHz. The output of the M divider is

also applied to the phase detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting

the VCO control voltage. Note that for some values of M (either

too high or too low), the PLL will not achieve lock. The output of

the VCO is scaled by a divider prior to being sent to each of

the LVCMOS output buffers. The divider provides a 50% out-

put duty cycle.

The programmable features of the ICS84021 support two input

modes to program the M divider and N output divider. The two

input operational modes are parallel and serial.

Figure 1 shows

the timing diagram for each mode. In parallel mode, the

nP_LOAD input is initially LOW. The data on inputs M0 through

M8 and N0 and N1 is passed directly to the M divider and

N output divider. On the LOW-to-HIGH transition of the nP_LOAD

input, the data is latched and the M divider remains loaded until

the next LOW transition on nP_LOAD or until a serial event oc-

curs. As a result, the M and N bits can be hardwired to set the