W

T

q

JA

W

I

VTT

W

I

VTT

ESR +

V

OUT

0.015

I

RIPPLE

0.75

[

I

OUT(max)

60 [mW]

TPS51116-EP

SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012

www.ti.com

Equation 25.

(25)

Thermal Design

Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and

sink directions generate power dissipation from the part. In the source phase, potential difference between

(26)

In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be

decreased.

is calculated by Equation 27:

(27)

actual power dissipation need to be considered for thermal design is an average of above value. Another power

consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN

supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN

supply can be estimated as 1.5 mA or less at normal operational conditions.

These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the

package is calculated by Equation 28,

(28)

where

•

•

•

This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced

PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this

die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat

sink/spread. The typical thermal resistance, 41.2°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land

with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number.

Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This

document is available at http:\\www.ti.com.

20

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