LM2736 datasheet(11/22 Pages) NSC

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Design Guide (Continued)

OUTPUT VOLTAGE

The output voltage is set using the following equation where

R2 is connected between the FB pin and GND, and R1 is

connected between V

O and the FB pin. A good value for R2

is 10k

Ω.

PCB Layout Considerations

When planning layout there are a few things to consider

when trying to achieve a clean, regulated output. The most

important consideration when completing the layout is the

close coupling of the GND connections of the C

IN capacitor

and the catch diode D1. These ground ends should be close

to one another and be connected to the GND plane with at

least two through-holes. Place these components as close to

the IC as possible. Next in importance is the location of the

GND connection of the C

OUT capacitor, which should be

near the GND connections of C

IN and D1.

There should be a continuous ground plane on the bottom

layer of a two-layer board except under the switching node

island.

The FB pin is a high impedance node and care should be

taken to make the FB trace short to avoid noise pickup and

inaccurate regulation. The feedback resistors should be

placed as close as possible to the IC, with the GND of R2

placed as close as possible to the GND of the IC. The V

OUT

trace to R1 should be routed away from the inductor and any

other traces that are switching.

High AC currents flow through the V

IN, SW and VOUT traces,

so they should be as short and wide as possible. However,

making the traces wide increases radiated noise, so the

designer must make this trade-off. Radiated noise can be

decreased by choosing a shielded inductor.

The remaining components should also be placed as close

as possible to the IC. Please see Application Note AN-1229

for further considerations and the LM2736 demo board as an

example of a four-layer layout.

LM2736 Datasheet(PDF) 11 Page - National Semiconductor (TI)

LM2736 Datasheet(HTML) 11 Page - National Semiconductor (TI)

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