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HV2221 Datasheet(PDF) 2 Page - Supertex, Inc

No. de pieza HV2221
Descripción Electrónicos  Low Charge Injection, 8-Channel, Unipolar, Negative High Voltage, Analog Switch
PDF  8 Pages
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Fabricante Electrónico  SUTEX [Supertex, Inc]
Página de inicio  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV2221 Datasheet(HTML) 2 Page - Supertex, Inc

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HV2221
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Ordering Information
Device
48-Lead LQFP
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
HV2221
HV2221FG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Parameter
Value
V
DD logic supply
-0.5V to +7.0V
V
PP-VNN differential supply
260V
V
PP positive supply
-0.5V to V
NN+260V
V
NN negative supply
+0.5V to -250V
Logic input voltage
-0.5V to V
DD +0.3V
Analog signal range
V
NN to VPP
Peak analog signal current/channel
4.5A
Storage temperature
-65°C to 150°C
Power dissipation
1.0W
Operating Conditions
Sym
Parameter
Value
V
DD
Logic power supply voltage
3.0V to 5.5V
V
PP - VNN
Supply voltage differential
240V
V
PP
Positive driver supply
+15V to +50V
V
NN
Negative high voltage supply
-100V to -225V
V
IH
High level input voltage
0.9V
DD to VDD
V
IL
Low-level input voltage
0V to 0.1V
DD
V
SIG
Analog signal voltage peak-to-peak
V
NN +10V to VPP -10V
T
A
Operating free air temperature
0OC to 70OC
Product Marking
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV2221FG
LLLLLLLLL
CCCCCCCC
AAA
48-Lead LQFP (FG)
Pin Configuration
48-Lead LQFP (FG)
(top view)
1
48
Notes:
1.
Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2.
V
SIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition.
3.
Rise and fall times of power supplies V
DD, VPP, and VNN should not be less than 1.0msec.
Package may or may not include the following marks: Si or



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