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HV57708 Datasheet(PDF) 3 Page - Supertex, Inc

No. de pieza HV57708
Descripción Electrónicos  32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs
PDF  7 Pages
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Fabricante Electrónico  SUTEX [Supertex, Inc]
Página de inicio  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV57708 Datasheet(HTML) 3 Page - Supertex, Inc

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Doc.# DSFP-HV57708
A061913
HV57708
DC Electrical Characteristics (Over recommended operating conditions unless otherwise noted)
Sym
Parameter
Min
Max
Units Conditions
I
DD
V
DD supply current
-
15
mA
V
DD = VDD max, fCLK = 8.0MHz
I
PP
High voltage supply current
-
100
µA
Outputs high
-
100
µA
Outputs low
I
DDQ
Quiescent V
DD supply current
-
100
µA
All V
IN = VDD
V
OH
High level output
HV
OUT
65
-
V
I
O = -15mA, VPP = +80V
Data out
V
DD -0.5
-
V
I
O = -100µA
V
OL
Low level output
HV
OUT
-
7.0
V
I
O = 12mA, VPP = +80V
Data out
-
0.5
V
I
O = 100µA
I
IH
High-level logic input current
-
1.0
µA
V
IH = VDD
I
IL
Low-level logic input current
-
-1.0
µA
V
IL = 0V
V
OC
High voltage clamp diode
-
1.0
V
I
OC = 1.0mA
AC Electrical Characteristics (T
A = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points])
Sym
Parameter
Min
Max
Units Conditions
f
CLK
Clock frequency
-
8.0
MHz
Per register
t
WL, tWH
Clock width high or low
62
-
ns
---
t
SU
Data set-up time before clock rises
10
-
ns
---
t
H
Data hold time after clock rises
15
-
ns
---
t
ON, tOFF
Time from latch enable to HV
OUT
-
500
ns
C
L = 15pF
t
DHL
Delay time clock to data high to low
-
70
ns
C
L = 15pF
t
DLH
Delay time clock to data low to high
-
70
ns
C
L = 15pF
t
DLE*
Delay time clock to LE low to high
25
-
ns
---
t
WLE
LE pulse width
25
-
ns
---
t
SLE
LE set-up time before clock rises
0
-
ns
---
* t
DLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR
output to stabilize).



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