TUSB5052 datasheet(19/82 Pages) TI

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3−7

Table 3−5. SUSP Pin Output

HUB BYPASSED

HUB SUSPENDED

FUNCTION SUSPENDED

IDLE BIT

SUSP OUTPUT

Yes

3.5

Reset Timing

There are two requirements for the reset signal timing. First, the minimum reset-pulse duration is 200

µs. At power

up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal is no

longer active (reset is active as long as it is less than 1.2 V). The second requirement is that the clock must be valid

during the last 180

µs of the reset window. The clock is valid when the oscillation on the XTAL2 pin exceeds 1.2 V p-p.

Figure 3−5 illustrates the relationships among the power, reset, and clock signals. Note that when using a 6-MHz

crystal and the on-chip oscillator, the clock signal may take several milliseconds following power up to ramp up and

become valid. Therefore, the reset window may need to be extended up to 10 ms or more to ensure that there is a

180-

µs overlap with a valid clock. Also, note that according to the USB specification, the chip has 100 ms to come

out of reset and be ready to respond to the host. The reset signal is inactive when it goes above 1.8 V.

CLK

Reset

3.3 V

1.8 V

1.2 V

0 V

VCC

90%

Reset Time < 100 ms

200

µs < Reset Time

> 180

µs

Figure 3−5. Relationship of Power, Reset, and Clock Signals

TUSB5052 Datasheet(PDF) 19 Page - Texas Instruments